Liste des instructions du Coldfire MCF5307

INSTRUCTION

SYNTAX

SIZE

OPERATION

ADD

Dy,<ea>x
<ea>y,Dx

32
32

Source+Destination->Destination

ADDA

<ea>y,ax

32

Source+Destination->Destination

ADDI

#<data>,Dx

32

Immediate_data+Destination->Destination

ADDQ

#<data>,<ea>x

32

Immediate_data+Destination->Destination

ADDX

Dy,Dx

32

Source+Destination+X->Destination

AND

Dy,<ea>x
<ea>y,Dx

32

Source&Destination->Destination

ANDI

#<data>,Dx

32

Immediate_data&Destination->Destination

ASL

Dx,Dy
#<data>,Dx

32

X/C<-(Dy<<Dx)<-0
X/C<-(Dy<<#<data>)<-0

ASR

Dx,Dy
#<data>,Dx

32

MSB->(Dy>>Dx)->X/C
MSB->(Dy>>#<data>)->X/C

Bcc

<label>

8,16

If Condition true, Then PC+dn->PC

BCHG

Dx,Dy
#<data>,<ea>Dx

8,32
8,32

~(<bit number> of destination)->Z
Z->Bit of destination

BCLR

Dx,Dy
#<data>,<ea>Dx

8,32
8,32

~(<bit number> of destination)->Z
0->Bit of destination

BRA

<label>

8,16

PC+dn->PC

BSET

Dx,Dy
#<data>,<ea>Dx

8,32
8,32

~(<bit number> of destination)->Z
1->Bit of destination

BSR

<label>

8,16

SP-4->PC;PC->(SP);PC+dn->PC

BTST

Dx,Dy
#<data>,<ea>Dx

8,32
8,32

~(<bit number> of destination)->Z

CLR

<ea>x

8,16,32

0->destination

CMPI

#<data>,Dx

32

Destination-Immediate Data

CMP

<ea>y,Dx

32

Destination-Source

CMPA

<ea>y,Ax

32

Destination-Source

CPUSH

(An)

32

Push and Invalidate Cache Line

DIVS

<ea>y,Dx

16
32

<ea>y->Dx {16b Remainder; 16b Quotient}
<ea>y->Dx {32b Quotient}
Note: signed operation

DIVU

<ea>y,Dx

16

<ea>y->Dx {16b Remainder; 16b Quotient}
<ea>y->Dx {32b Quotient}
Note: unsigned operation

EOR

Dy,<ea>x

32

Source^Destination->Destination

EORI

#<data>,Dx

32

Immediate_data^Destination->Destination

EXT

Dx
Dx

8->16
16->32

Sign-Extend Destination -> Destination

EXTB

Dx

8->32

Sign-Extend Destination -> Destination

HALT

-

-

Enter halted state

JMP

<ea>

-

Adress of <ea> -> PC

JSR

<ea>

-

SP-4->PC;PC->(SP);<ea>->PC

LEA

<ea>y,Ax

32

<ea>->An

LINK

Ax,#<data>

16

SP-4->SP;Ax->(SP);SP->Ax;SP+d16->SP

LSL

Dx,Dy
#<data>,Dx

32
32

X/C<-(Dy<<Dx)<-0
X/C<-(Dy<<#<data>)<-0

LSR

Dx,Dy
#<data>,Dx

32
32

0->(Dy>>Dx)->X/C
0->(Dy>>#<data>)->X/C

MAC

Rw,Rx,<shift>

16x16+32->32
32x32+32->32

ACC+(RwxRx){<<1|>>1}->ACC

MACL

Rw,Rx,<shift>,
<ea>,Ry

16x16+32->32
32x32+32->32

ACC+(RwxRx){<<1|>>1}->ACC;
(<ea>{&MASK})->Ry

MOVE

<ea1>,<ea2>

8,16,32

<ea1>-><ea2>

MOVE-from-ACC

ACC,Rx

32

ACC->Rx

MOVE-from-CCR

Dx

16

CCR->Dx

MOVE-from-MACSR

MACSR,Rx
MACSR,CCR

32
8

MACSR->Rx
MACSR->CCR

MOVE-from-MASK

MASK,Rx

32

MASK->Rx

MOVE-from-SR

Dx

16

SR->Destination

MOVE-to-ACC

Rx,ACC,#<data>,
ACC

32
32

Rx->ACC
#<data>->ACC

MOVE-to-CCR

Dn,CCR,#<data>,
CCR

16

Rx->CCR
#<data>->CCR

MOVE-to-MACSR

Rn,MACSR,#<data>,
MACSR

32

Rx->MACSR
#<data>->MACSR

MOVE-to-MASK

Rn,MASK,#<data>,
MASK

32
32

Rx->MASK
#<data>->MASK

MOVE-to-SR

Rn,SR,#<data>,
SR

16

Source->SR

MOVEA

<ea>y,Ax

16,32->32

Source->Destination

MOVEC

Rn,Rc

32

Rn->Rc

MOVEM

list,<ea>x
<ea>y,list

32
32

Listed Registers -> Destination
Source -> Listed Registers

MOVEQ

#<data>,Dx

8->32

Sign-extended Imm. Data -> Destination

MSAC

Rw,Rx,<shift>

16x16+32->32
32x32+32->32

ACC-(RwxRx){<<1|>>1}SF->ACC

MSACL

Rw,Rx,<shift>,
<ea>,Ry

16x16+32->32
32x32+32->32

ACC-(RwxRx){<<1|>>1}SF->ACC;
(<ea>{&MASK})->Ry

MULS

<ea>y,Dx

16x16->32
32x32->32

Source x Destination -> Destination
Note: signed operation

MULU

<ea>y,Dx

16x16->32
32x32->32

Source x Destination -> Destination
Note: unsigned operation

NEG

<ea>x

32

0-Destination->Destination

NEGX

<ea>x

32

0-Destination-X->Destination

NOP

-

-

PC+2->PC; Sync Pipeline

NOT

<ea>

32

~Destination->Destination

OR

Dy,<ea>x
<ea>y,Dx

32

Source|Destination->Destination

ORI

#<data>,Dx

32

Immediate_data|Destination->Destination

PEA

<ea>

32

SP-4->SP; Adress of <EA>->(SP)

PULSE

-

-

Set PST=$4

REMS

<ea>y,Dx

32

<ea>y->Dx{32 bit remainder}
Note: signed operation

REMU

<ea>y,Dx

32

<ea>y->Dx{32 bit remainder}
Note: unsigned operation

RTE

-

-

(SP+2)->SR; (SP+4)->PC; SP+8->SP

RTS

-

-

(SP)->PC; SP+4->SP

Scc

Dx

8

If Condition True, Then 1's->Destination
Else 0's->Destination

STOP

#<data>

16

Immediate Data -> SR;
Enter Stopped State

SUB

Dy,<ea>x
<ea>y,Dx

32
32

Destination-Source->Destination

SUBA

<ea>,Ax

32

Destination-Source->Destination

SUBI

#<data>,Dx

32

Destination-Immediate Data->Destination

SUBQ

#<data>,<ea>x

32

Destination-Immediate Data->Destination

SUBX

Dy,Dx

32

Destination-Source-X->Destination

SWAP

Dn

16

MSW of Dn <-> LSW of Dn

TRAP

-

-

SP-4->SP; PC->(SP); SP-2->SP; SR->(SP);
SP-2->SP;Format->(SP);Vector Adr->PC

TRAPF

-
#<data>

-
16
32

PC+2->PC; PC+4->PC; PC+6->PC

TST

<ea>y

8,16,32

Set Integer Condition Codes

UNLK

Ax

32

Ax->SP; (SP)->Ax; SP+4->SP

WDDATA

<ea>

8,16,32

<ea>->DDATA port

WDEBUG

<ea>

16

<ea>->Debug Module

INSTRUCTION	SYNTAX	SIZE	OPERATION
ADD	Dy,<ea>x <ea>y,Dx	32 32	Source+Destination->Destination
ADDA	<ea>y,ax	32	Source+Destination->Destination
ADDI	#<data>,Dx	32	Immediate_data+Destination->Destination
ADDQ	#<data>,<ea>x	32	Immediate_data+Destination->Destination
ADDX	Dy,Dx	32	Source+Destination+X->Destination
AND	Dy,<ea>x <ea>y,Dx	32	Source&Destination->Destination
ANDI	#<data>,Dx	32	Immediate_data&Destination->Destination
ASL	Dx,Dy #<data>,Dx	32	X/C<-(Dy<<Dx)<-0 X/C<-(Dy<<#<data>)<-0
ASR	Dx,Dy #<data>,Dx	32	MSB->(Dy>>Dx)->X/C MSB->(Dy>>#<data>)->X/C
Bcc	<label>	8,16	If Condition true, Then PC+dn->PC
BCHG	Dx,Dy #<data>,<ea>Dx	8,32 8,32	~(<bit number> of destination)->Z Z->Bit of destination
BCLR	Dx,Dy #<data>,<ea>Dx	8,32 8,32	~(<bit number> of destination)->Z 0->Bit of destination
BRA	<label>	8,16	PC+dn->PC
BSET	Dx,Dy #<data>,<ea>Dx	8,32 8,32	~(<bit number> of destination)->Z 1->Bit of destination
BSR	<label>	8,16	SP-4->PC;PC->(SP);PC+dn->PC
BTST	Dx,Dy #<data>,<ea>Dx	8,32 8,32	~(<bit number> of destination)->Z
CLR	<ea>x	8,16,32	0->destination
CMPI	#<data>,Dx	32	Destination-Immediate Data
CMP	<ea>y,Dx	32	Destination-Source
CMPA	<ea>y,Ax	32	Destination-Source
CPUSH	(An)	32	Push and Invalidate Cache Line
DIVS	<ea>y,Dx	16 32	<ea>y->Dx {16b Remainder; 16b Quotient} <ea>y->Dx {32b Quotient} Note: signed operation
DIVU	<ea>y,Dx	16	<ea>y->Dx {16b Remainder; 16b Quotient} <ea>y->Dx {32b Quotient} Note: unsigned operation
EOR	Dy,<ea>x	32	Source^Destination->Destination
EORI	#<data>,Dx	32	Immediate_data^Destination->Destination
EXT	Dx Dx	8->16 16->32	Sign-Extend Destination -> Destination
EXTB	Dx	8->32	Sign-Extend Destination -> Destination
HALT	-	-	Enter halted state
JMP	<ea>	-	Adress of <ea> -> PC
JSR	<ea>	-	SP-4->PC;PC->(SP);<ea>->PC
LEA	<ea>y,Ax	32	<ea>->An
LINK	Ax,#<data>	16	SP-4->SP;Ax->(SP);SP->Ax;SP+d16->SP
LSL	Dx,Dy #<data>,Dx	32 32	X/C<-(Dy<<Dx)<-0 X/C<-(Dy<<#<data>)<-0
LSR	Dx,Dy #<data>,Dx	32 32	0->(Dy>>Dx)->X/C 0->(Dy>>#<data>)->X/C
MAC	Rw,Rx,<shift>	16x16+32->32 32x32+32->32	ACC+(RwxRx){<<1\|>>1}->ACC
MACL	Rw,Rx,<shift>, <ea>,Ry	16x16+32->32 32x32+32->32	ACC+(RwxRx){<<1\|>>1}->ACC; (<ea>{&MASK})->Ry
MOVE	<ea1>,<ea2>	8,16,32	<ea1>-><ea2>
MOVE-from-ACC	ACC,Rx	32	ACC->Rx
MOVE-from-CCR	Dx	16	CCR->Dx
MOVE-from-MACSR	MACSR,Rx MACSR,CCR	32 8	MACSR->Rx MACSR->CCR
MOVE-from-MASK	MASK,Rx	32	MASK->Rx
MOVE-from-SR	Dx	16	SR->Destination
MOVE-to-ACC	Rx,ACC,#<data>, ACC	32 32	Rx->ACC #<data>->ACC
MOVE-to-CCR	Dn,CCR,#<data>, CCR	16	Rx->CCR #<data>->CCR
MOVE-to-MACSR	Rn,MACSR,#<data>, MACSR	32	Rx->MACSR #<data>->MACSR
MOVE-to-MASK	Rn,MASK,#<data>, MASK	32 32	Rx->MASK #<data>->MASK
MOVE-to-SR	Rn,SR,#<data>, SR	16	Source->SR
MOVEA	<ea>y,Ax	16,32->32	Source->Destination
MOVEC	Rn,Rc	32	Rn->Rc
MOVEM	list,<ea>x <ea>y,list	32 32	Listed Registers -> Destination Source -> Listed Registers
MOVEQ	#<data>,Dx	8->32	Sign-extended Imm. Data -> Destination
MSAC	Rw,Rx,<shift>	16x16+32->32 32x32+32->32	ACC-(RwxRx){<<1\|>>1}SF->ACC
MSACL	Rw,Rx,<shift>, <ea>,Ry	16x16+32->32 32x32+32->32	ACC-(RwxRx){<<1\|>>1}SF->ACC; (<ea>{&MASK})->Ry
MULS	<ea>y,Dx	16x16->32 32x32->32	Source x Destination -> Destination Note: signed operation
MULU	<ea>y,Dx	16x16->32 32x32->32	Source x Destination -> Destination Note: unsigned operation
NEG	<ea>x	32	0-Destination->Destination
NEGX	<ea>x	32	0-Destination-X->Destination
NOP	-	-	PC+2->PC; Sync Pipeline
NOT	<ea>	32	~Destination->Destination
OR	Dy,<ea>x <ea>y,Dx	32	Source\|Destination->Destination
ORI	#<data>,Dx	32	Immediate_data\|Destination->Destination
PEA	<ea>	32	SP-4->SP; Adress of <EA>->(SP)
PULSE	-	-	Set PST=$4
REMS	<ea>y,Dx	32	<ea>y->Dx{32 bit remainder} Note: signed operation
REMU	<ea>y,Dx	32	<ea>y->Dx{32 bit remainder} Note: unsigned operation
RTE	-	-	(SP+2)->SR; (SP+4)->PC; SP+8->SP
RTS	-	-	(SP)->PC; SP+4->SP
Scc	Dx	8	If Condition True, Then 1's->Destination Else 0's->Destination
STOP	#<data>	16	Immediate Data -> SR; Enter Stopped State
SUB	Dy,<ea>x <ea>y,Dx	32 32	Destination-Source->Destination
SUBA	<ea>,Ax	32	Destination-Source->Destination
SUBI	#<data>,Dx	32	Destination-Immediate Data->Destination
SUBQ	#<data>,<ea>x	32	Destination-Immediate Data->Destination
SUBX	Dy,Dx	32	Destination-Source-X->Destination
SWAP	Dn	16	MSW of Dn <-> LSW of Dn
TRAP	-	-	SP-4->SP; PC->(SP); SP-2->SP; SR->(SP); SP-2->SP;Format->(SP);Vector Adr->PC
TRAPF	- #<data>	- 16 32	PC+2->PC; PC+4->PC; PC+6->PC
TST	<ea>y	8,16,32	Set Integer Condition Codes
UNLK	Ax	32	Ax->SP; (SP)->Ax; SP+4->SP
WDDATA	<ea>	8,16,32	<ea>->DDATA port
WDEBUG	<ea>	16	<ea>->Debug Module