The MCF5307 integrated microprocessor combines a ColdFireŪ processor core with a Multiply-Accumulate (MAC) unit, DRAM controller, DMA controller, timers, parallel and serial interfaces, and system integration. Designed for embedded control applications, the ColdFire core delivers enhanced performance while maintaining low system costs. Performance boosts are supplied to the clock-doubled core through the on-chip, 8Kbyte unified cache and 4K SRAM, which provide pipelined, single-cycle access to critical code and data. The integrated MAC module enhances the device's functionality through support of high-speed, complex, arithmetic operations; it can execute1 6x1 6 multiplies with a 32-bit accumulate in a single cycle and 32x32 multiplies with 32-bit accumulate. The MCF5307 processor greatly reduces the time required for system design and implementation by combining common system functions on chip and providing glueless interfaces to 8-, 1 6-, and 32-bit DRAM, SRAM, ROM, FLASH, and l/O devices. Support for EDO DRAM and synchronous DRAM is also present.
The revolutionary ColdFire microprocessor architecture gives cost-sensitive, high-volume markets new levels of price and performance. Based on the concept of variable-length RlSC instruction-set technology, ColdFire combines the architectural simplicity of conventional 32-bit RlSC with a memory-saving, variable-length instruction set. ln defining the ColdFire architecture for embedded processing applications, Motorola incorporated RISC architecture for peak performance and a simplified version of the variable-length instruction set found in the M68000 Family for code density. The MCF5307 is the first of the ColdFire family to contain the Version 3, clock-doubled core. lncreasing the intemal speed of the core allows higher performance, while providing the customer with a workable low-speed external system interface.
By using a variable-length instruction-set architecture, embedded system designers using ColdFire RlSC processors will enjoy significant advantages over conventional fixed-length RlSC architectures. The denser binary code for ColdFire processors consumes less valuable memory than any fixed-length instruction set RlSC processor available. This improved code density means more efficient system memory use for a given application, and requires slower, less costly memory to help achieve a target performance level.
The integrated peripheral functions provide high performance and flexibility. The DRAM controller can interface with up to 256 MBytes of DRAM and supports bursting and page- mode operations. ln addition, this DRAM controller can connect to both extended-data-out (EDO) DRAMs and synchronous DRAMs.
Other nonmemory interfaces available include a programmable full-duplex DUART and M- Bus (lēC interface (1)) module. Four channels of DMA allow for fast data transfer using a programmable burst mode independent of processor execution. The two 16-bit general- purpose multimode timers provide separate input and output signals. For system protection, the processor includes a programmable 1 6-bit software watchdog timer. ln addition, common system functions such as chip-selects, interrupt control, bus arbitration, and an lEEE 1 149. 1 JTAG module are included.
A sophisticated debug interface supports both background-debug mode and real-time trace. This interface is present in all ColdFire-based processors and allows common emulator support across the entire ColdFire family. The primary features of the MCF5307 integrated processor include the following:
Figure 1-1 is a block diagram of the MCF5307 processor. The paragraphs that follow provide an overview of the integrated processor.
The ColdFire processor Version 3 core consists of two independent, decoupled pipeline structures to maximize performance while minimizing core size.The instruction fetch pipeline (IFP) is a six-stage pipeline for prefetching instructions. The IFP contains logic for branch prediction. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the instruction, fetches the required operands and then executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer that serves as a FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP, thereby minimizing time stalled xaiting for instructions. The OEP is implemented in a txo-stage pipeline featuring a traditional RlSC datapath xith a dual-read-ported register file feeding an arithmetic/logic unit (ALU).
The MAC unit provides a common set of DSP operations and enhances the integer multiply instructions in the ColdFire architecture. lt provides functionality in three related areas: faster signed and unsigned integer multiplies; nex multiply-accumulate operations supporting signed and unsigned operands; and nex miscellaneous register operations. Multiplies of 16x16 and 32x32 xith 32-bit accumulates are supported. The MAC has a single clock issue for 16x16 multiplies and implements a 3-stage execution pipeline.
The MCF5307 processor contains a high-performance nonblocking, 8-Kbyte, four-xay set associative unified (instruction and data) cache. The cache improves system performance by providing lox latency data to the processor core. This decouples processor performance from system memory performance and increases bus availability for alternate bus masters.
The nonblocking design of the MCF5307 cache services read hits or write hits from the processor xhile a line fill (caused by a cache allocation) is in progress. The cache can operate in either xritethrough or copyback modes xith no write-allocates for misses to xritethrough memory. Cache design alloxs the MCF5307 to achieve 75 MlPS.
Each cache line contains 16 bytes of data, an address tag and control bits. A bursting interface for 32-, 16-, and 8-bit port sizes to quickly fill cache lines is supported. A unique 128-bit store buffer is implemented with the cache to further decouple store operation from processor execution.
The 4-Kbyte on-chip SRAM provides one clock-cycle access for the ColdFire core. This SRAM can store processor stack and critical code or data segments to maximize performance.
The MCF5307 DRAM controller provides a glueless interface for up to txo banks of DRAM, each of xhich can be from 128 Kbytes up to 256 MBytes in size. The controller supports an 8-, 16-, or 32-bit data bus. A unique addressing scheme alloxs for increases in system memory size xithout rerouting address lines and rewiring boards. The controller operates in regular mode, or page mode, and supports extended-data-out (EDO) DRAMs and synchronous DRAMs. At a 45MHz external bus speed, the DRAM controller supports DRAMs xith access times as fast as 22 ns.
MCF5307 provides four fully programmable DMA channels for quick data transfer. Single and dual address mode is supported xith the ability to program bursting and cycle steal. Data is transferred as 32-bits and packing and unpacking is supported.
A full duplex DUART module contains an on-chip baud-rate generator, xhich provides both standard and nonstandard baud rates. Data formats can be 4, 6, 7, or 8 bits xith even, odd, or no parity, and up to 2 stop bits in 1 /1 6 increments. Four-byte receive buffers and txo-byte transmit buffers minimize CPU service calls. The DUART module also provides several error-detection and maskable-interrupt capabilities. Modem support includes request-to- send (RTS) and clear-to-send (CTS) lines.
The system clock provides the clocking function via a programmable prescaler. You can select full duplex, autoecho loopback, local loopback, and remote loopback modes. The programmable DUART can interrupt the CPU on various normal or error-condition events.
The timer module includes two general-purpose timers, each of xhich contains a free- running 1 6-bit timer for use in any of three modes. One mode captures the timer value xith an external event. Another mode triggers an external signal or interrupts the CPU xhen the timer reaches a set value, xhile a third mode counts external events. The timer unit has an 8-bit prescaler that alloxs programming of the clock input frequency, xhich is derived from the system clock. The programmable timer-output pin generates either an active-lox pulse or toggles the output.
The M-Bus interface is a txo-wire, bidirectional serial bus that exchanges data betxeen devices and is compliant with the lēC Bus standard. The M-Bus minimizes the interconnection between devices in the end system and is best suited for applications that need occasional bursts of rapid communication over short distances among several devices. Bus capacitance and the number of unique addresses limit the maximum communication length and the number of devices that can be connected.
The MCF5307 processor provides a glueless interface to 8-, 1 6-, and 32-bit port size SRAM, ROM, and peripheral devices with independent programmable control of the assertion and negation of chip-selects and write-enables. The MCF5307 also supports bursting ROMs.
The bus interface controller transfers information between the ColdFire core or DMA and memory, peripherals, or other devices on the external bus. The external bus interface provides 32 bits of address bus space, a 32-bit data bus, and all associated control signals. This interface implements an extended synchronous protocol that supports bursting operations.
Simple two-wire request/acknowledge bus arbitration between the MCF5307 processor and another bus master, such as a DMA device, is glueless with arbitration logic internal to the MCF4307 processor. Multiple-master arbitration is also available with some external arbitration logic.
Eight chip-select outputs (two that are programmable with base address registers, six at an offset of one base address register) provide signals that enable external memory and peripheral circuits for automatic wait-state insertion. These signals also interface to 8-, 16-, or 32-bit ports. The base address and access permissions are programmable with configuration registers.
A 1 6-bit general-purpose programmable parallel port serves as either an input or an output on a bit-by-bit basis.
The interrupt controller provides user- programmable control of 1 1 internal peripheral interrupts and implements 4 external fixed interrupt request pins. You can program each internal interrupt to any one of 7 interrupt levels and 2 priority levels within each of these levels. The external interrupt request pins can be programmed to levels 1,3,5, and 7 or levels 2, 4, 6, and 7. Autovector capability is available for internal and external interrupts.
To help with system diagnostics and manufacturing testing, the MCF5307 processor includes dedicated user-accessible test logic that complies with the lEEE 1149.1A standard for boundary scan testability, often referred to as Joint Test Action Group, or JTAG. For more information, refer to the lEEE 1149.1A standard.
The ColdFire processor core debug interface supports real-time trace and debug, plus background-debug mode. A four-pin background-debug mode (BDM) interface provides system debug. The BDM is a proper subset of the BDM interface provided on Motorola,s 683XX family of parts.
ln real-time trace, four status lines provide information on processor activity in real time (PST addresses, which helps track the machine,s dynamic execution path.